Lab: Flip Flops and Latches
CSC 211 - Computer Organization & Architecture - Weinman
- Summary:
- You will describe and implement a hierarchy of memories,
from latches to flip flops.
Preparation
Launch logisim with the following command:
-
java -jar /home/weinman/courses/CSC211/labs/logisim.jar &
Background
For combinational logic, which is a simple mapping of logical inputs
to outputs, we can talk about the truth table as the function
specifying the input/output mapping. For sequential logic, the outputs
become inputs. However, we can still talk about how the state maps
to updated values in something we call the characteristic table,
sequential logic's analog to the truth table of combinational logic.
Other than listing the current value of an output on the left (with
the inputs), and the updated/next value of the output on the right
(as an output), there is no clearly identified standard for distinguishing
these before/after values. Some use say Q and Qn or perhaps
Qnext to distinguish the "after" or next state of
an output Q. We will take that approach in what follows.
Exercises
A. S-R Latch
-
Using Figure C.8.1 from your text (p. C-50), record
(on paper or computer) your completion of the characteristic table
for the so-called S-R latch. (Q bar did not convert to HTML well.)
| S | R | Q | [`(Q)] | Qnext | [`(Q)]next |
|
| 0 | 0 | 0 | 1 | | |
| 0 | 0 | 1 | 0 | | |
| 1 | 0 | 0 | 1 | | |
| 1 | 0 | 1 | 0 | | |
| 0 | 1 | 0 | 1 | | |
| 0 | 1 | 1 | 0 | | |
Note that we don't include any rows where S=R=1 because bad things
can happen (see PH C.11).
- In your main Logisim project, create a subcircuit called s-r-latch.
In that subcircuit, implement a simluation of Figure C.8.1. To avoid
accidental oscillations, build your diagram in this order
- Gates
- Input pins (label them)
- Output pins (label them)
- Connect input pins to gates
- Connect output gates to output pins
- Connect gate outputs to gate inputs (diagonal wires in the figure)
- Test the various configurations of S and R to verify your characteristic
table.
- Save your project as D-flip-flop.circ, lest the NullPointerException
gremlin eat your work.
B. D Latch
- Using Figure C.8.2 from your text (p. C-52), record your completion
of the characteristic table for the D latch. (I recommend labeling
the R and S inputs of the S-R Latch component and using your
table from A.1 to help you.)
| C | D | Q | Qnext |
|
| 0 | 0 | 0 | |
| 0 | 0 | 1 | |
| 0 | 1 | 0 | |
| 0 | 1 | 1 | |
| 1 | 0 | 0 | |
| 1 | 0 | 1 | |
| 1 | 1 | 0 | |
| 1 | 1 | 1 | |
- In the same project, create a new subcircuit called d-latch.
Drop one version of your s-r-latch into this new subcircuit
and wire the rest to match Figure C.8.2.
- Set the properties of your AND gates so they have only two inputs,
with one of them having a negated input. (Thus, you should not use
a NOT gate in your drawing.)
- Label your input and output pins.
- Test the various configurations of C and D to verify your characteristic
table.
- Save your work.
C. D Flip Flop
- In the already extant main subcircuit, create a D flip-flop
to match Figure C.8.4 (p. C-53) by reusing the d-latch subcircuit.
- Label your input and output pins.
- Be careful! They slyly flip labels for D and
C on their latches!
- Test the various configurations of C and D to verify the flip-flop
as a memory element.
- What will happen if you raise D, then raise C, but then lower
D before you lower C? Verify your prediction.
Copyright © 2015 Jerod
Weinman.
This work is licensed under a Creative
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