CSC 211: Exam 3

1 Learning Outcomes

At the end of this unit you should be able to:

For a single-cycle datapath:
- Identify the portions of the datapath that are active on any given instruction
- Give the necessary control signals for a particular instruction
- Identify the critical path and minimum latency of an instruction, given the latency of individual functional units on the datapath
For a single-issue pipelined datapath:
- Identify data and control hazards
- Identify opportunities for data forwarding
- Stall the pipeline when necessary
- Write control logic for forwarding hardware
- Measure throughput and latency
- Generate execution schedules (clock cycle diagrams) for the standard MIPS architecture
- Explain how exceptions are handled
Describe the 1-bit and 2-bit branch predictors
Measure the performance of various branch prediction or handling schemes
Find instructions that are safe to fill the branch delay slot
Name conditions that could generate exceptions
Know the difference between static multiple issue, in-order and out-of-order superscalar processing
Schedule static multiple issue processors optimally
Unroll loops to increase performance of multiple issue processors

The following exercises are from Patterson and Hennessy (Fifth Edition)