CSC 211: Exam 4

CSC 211 - Computer Organization and Architecture - Weinman

1  Learning Outcomes

• Distinguish between temporal and spatial locality
• Describe and explain the impact on miss rate as the cache block size changes
• Relate the size of the tag and index to cache size (i.e., number of lines ands block size) given the address size or memory size
• Explain the trade-offs between direct-mapped, set associative, and fully associative caches
• Explain the impact of miss rate, hit rate, hit time, and miss penalty on performance
• Given appropriate system information, calculate the
  • average memory access time (AMAT),
  • memory stall cycles
  • total cycles per instruction (CPI), and
  • millions of instructions per second (MIPS)
  for a multi-level memory hierarchy
• Distinguish between compulsory, capacity, and conflict cache misses
• Simulate a working cache given a request stream and eviction policy
• Relate the address fields or size, memory size, page size, virtual page number, and physical page number
• Translate a virtual page number to a physical page number given a page table and/or TLB
• State the meaning of the valid bit in the TLB and the page table
• Appropriately place/locate each component of the memory hierarchy in a computer
• Use the dynamic power equation to relate properties (i.e. capacitive load, voltage, frequency) of different single core or multicore processors
• Use Amdahl's law to calculate the speedup or execution time due to a performance improvement
• Distinguish between sequential, serial, parallel, and concurrent tasks/execution
• Characterize the differences between vector, superscalar, and multicore architectures
• State the trade-offs between different types of multithreading
• Identify and characterize the performance impact of false sharing
• Use the MIPS sc/ll primitives to create atomic read-modify-write sequences

2  Study Problems

Chapter 1

5-7, 9, 11, 12, 15

Chapter 4

1-16, 18

Chapter 5

1, 2.1-2.5, 3, 5, 6, 7.1-7.3, 11, 12.1, 13

Chapter 6

6, 7, 9