Sequential Logic

• Summary: For this mini lab you will implement a variety of memory circuits.

• Collaboration: You will work with a randomly assigned partner during class.

• Submitting: You do not need to turn in any work for this lab. If you are unable to finish all of the exercises during class time, you should complete this work on your own.

Preparation

Start Logisim with the following command:

$ java -jar /home/curtsinger/shared/logisim.jar

Background

For combinational logic, which is a simple mapping of logical inputs to outputs, we can talk about the truth table as the function specifying the input/output mapping. For sequential logic, the outputs become inputs. However, we can still talk about how the state maps to updated values in something we call the characteristic table, sequential logic’s analog to the truth table of combinational logic.

Other than listing the current value of an output on the left (with the inputs), and the updated/next value of the output on the right (as an output), there is no clearly identified standard for distinguishing these before/after values. We will use $Q$ and $Q_\text{next}$ to refer to the current and next states of an output $Q$ for this lab.

Helpful Tips

Some circuits can oscillate their assertion status (with regular stability, as in a clock, or wildly in other cases). We do not want our latches and flip-flops to oscillate, but Logisim sometimes has trouble dealing with the loopy connections correctly.

If you end up with all red wires you can sometimes resolve the issue by selecting the “Reset Simulation” option from the “Simulate” menu. Some errors stop the simulation, so selecting “Simulation Enabled” is occasionally necessary.

Exercise 1: S-R Latch

1. Use Figure B.8.1 from your text to complete the characteristic table for an S-R latch. Record your answers on paper or computer.

   $S$	$R$	$Q$	$\bar{Q}$	$Q_\text{next}$	$\bar{Q}_\text{next}$
   0	0	0	1
   0	0	1	0
   1	0	0	1
   1	0	1	0
   0	1	0	1
   0	1	1	0

   Note that we don’t include any rows for $S=R=1$ because bad things can happen (see Section B.11 of Patterson & Hennessy) .

   In order for your characteristic table to stabilize without infinite oscillation, you must perform your “updates” to $Q_\text{next}$ and $\bar{Q}_\text{next}$ asynchronously. For example, when calculating $\bar{Q}_\text{next}$, use the updated value $Q_\text{next}$ for $Q$. In other words, perform only one update (either to $Q_\text{next}$ or $\bar{Q}_\text{next}$) at a time, and use the updated value of one to then calculate the updated value of the other.

2. Create a Logisim project, then build an S-R latch in a subcircuit called “s-r latch”. For your latch to work (avoiding oscillations), you will need to build your circuit in this specific order:

   • Gates
   • Input pins (labeled)
   • Output pins (labeled)
   • Connect input pins to gates
   • Connect output pins to gate outputs
   • Connect gate outputs to gate inputs

3. Test the various configurations of S and R to verify your characteristic table

4. Save your Logisim project (and save frequently!)

Exercise 2: D Latch

1. Complete the characteristic table for a D latch:

   $C$	$D$	$Q$	$Q_\text{next}$
   0	0	0
   0	0	1
   0	1	0
   0	1	1
   1	0	0
   1	0	1
   1	1	0
   1	1	1

   I recommend labeling the R and S inputs of the S-R Latch component and using your table from Exercise 1.a to help you.

2. In the same Logisim project, create a subcircuit called “d latch”. Drop your “s-r latch” subcircuit into this circuit and add the additional inputs, outputs, and wires to implement a D latch.

3. Test the various settings of $C$ and $D$ to verify your characteristic table; you may want to consult Figure B.8.3 as well.

4. Save!

Exercise 3: D Flip-Flop

1. In the “main” subcircuit, build a D flip-flop with two D latches (see Figure B.8.4).

   • Be sure to label your input and output pins
   • Be Careful! The book flips their $C$ and $D$ inputs between Figures B.8.2 and B.8.4; mind your subcircuit’s input pin labels.

2. Test the various configurations of $C$ and $D$ to verify your flip-flop is behaving correctly as a memory element; you may want to consult Figure B.8.5.

3. Without using your Logisim circuit, predict what will happen if you raise $D$, then raise $C$, but then lower $D$ before lowering $C$? Verify your prediction with Logisim.

Extra: Rising Edges

The D flip-flop in the textbook is designed to update on a falling edge. Suppose we wanted a system that updated on a rising edge.

1. Discuss how the D flip-flop would need to change in order to update on the rising edge.

2. Copy the falling edge D flip-flop from your “main” subcircuit into a new subcircuit called “risingDFF”.

3. Implement the changes you discussed in part a in your new subcircuit.

4. Test the various configurations of $C$ and $D$ to verify your flip-flop still behaves as a memory element, but with a rising-edge trigger.

Copyright © 2018, 2019, 2020 Charlie Curtsinger and Jerod Weinman

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