CSC 211: Exam 4

1 Learning Outcomes

At the end of this unit you should be able to:

Distinguish between temporal and spatial locality
Describe and explain the impact on miss rate as the cache block size changes
Relate the size of the tag and index to cache size (i.e., number of lines ands block size) given the address size or memory size
Explain the trade-offs between direct-mapped, set associative, and fully associative caches
Explain the impact of miss rate, hit rate, hit time, and miss penalty on performance
Given appropriate system information, calculate the
1. average memory access time (AMAT),
2. memory stall cycles, and
3. total cycles per instruction (CPI),
for a multi-level memory hierarchy
Distinguish between compulsory, capacity, and conflict cache misses
Simulate a working cache given a request stream and eviction policy
Relate the address fields or size, memory size, page size, virtual page number, and physical page number
Translate a virtual page number to a physical page number given a page table and/or TLB
State the meaning of the valid bit in the TLB and the page table
Appropriately place/locate each component of the memory hierarchy in a computer
Use Amdahl's law to calculate the speedup or execution time due to a performance improvement
Distinguish among sequential, serial, parallel, and concurrent tasks/execution
Characterize the differences among parallel architectures (i.e., vector, superscalar, and multicore)
State the trade-offs between different types of multithreading

The following exercises are from Patterson and Hennessy.

Fifth Edition

Sixth Edition