Latches and Flip-Flops

Due: 5 pm Thursday 27 February 2025
Summary: In this lab, you will build your understanding of memory elements by building an S–R latch, a D latch, and a D-type flip-flop. In the last step, you can implement either a simple register file or a “neat” light display using latches.
Collaboration: You will work during lab in randomly assigned pairs. You must complete the work together in these groups, whether during or after the scheduled lab time.
Submitting: After completing each exercise, show your completed circuit to the instructor or a course mentor. If you are unable to complete the lab during class time, schedule a time during office hours to demonstrate each of your circuits.

Process Guide

In steps one and two, you will build an S-R latch and then a D latch from your S-R latch, before building D flip-flop. Since you need two D latches (and therefore two S-R latches) to build a D flip-flop, I recommend the following layout strategy.

Step 1
- Place your chips and select gates close enough that you can use flat jumpers to make nearly all the connections.
- Build the first S-R latch on a single breadboard column, using only TTL pins on the left side of the chip.
- Ask the mentor or instructor to sign off on your circuit.
- Now that you have verified this circuit is correct, duplicate it on the right side of the chip, where all the connections should be only one row lower than on the left side. (If you used the proper length-specific colored jumpers, it should be straightforward to copy.)
- Test your second S-R latch.
Step 2
- Modify your left-side S-R latch to be a D latch, once again using only connections on the left side.
- Ask the mentor or instructor to sign off on your circuit.
- Now that you have verified this circuit is correct, duplicate it on the right side of the chip, where again all the connections should be only one row lower than on the left side.
- Test your second D latch.
Step 4
- Re-arrange your connections among your two D latches to create a single D flip-flop.

Step 1: Build an S–R latch

Build an S–R latch on yor protoboard using the following circuit diagram:

Test your S–R latch. How do you know it is storing a value?

Have the instructor or mentor sign off on your S-R latch, then build your second S-R latch copy on the right-side of your TTL.

Step 2: Build a D latch

Add the necessary gates to turn your S–R latch into a D latch. Recall that a D latch has two inputs and two outputs:

input \(D\): The data value that should be stored in the latch
input \(C\): The clock input. When this pin is high, the value on \(D\) is stored in the latch. If \(C\) is low, then the stored value should not change. Note that this input is sometimes called \(E\), for “enable.”
output \(Q\) G: The stored value in the latch
output \(\bar{Q}\): The inverse of the stored value

Test your D latch to verify that it stores the correct value, and only updates the stored value when the clock input is high.

Have the instructor or mentor sign off on your D latch before moving on to the next step.

Step 3: Drive your D latch with a clock

Connect the \(C\) input of your D latch to the clock signal on the left side of your protoboard. You should hook a logic indicator light up to the clock input so you can monitor it. Set your clock on the TTL option, square wave, and a low frequency (Hz, not KHz, and 1, not 10 or 100).

With the clock set slow enough, you should be able to watch the value on \(D\) update the latch state only when the clock is high.

What happens when you change \(D\) while \(C\) is still high?

Step 4: Build a D flip-flop

Build a second D latch and connect it to your first D latch to build an edge-triggered flip-flop. The following figure shows a D flip-flop that stores an input value on the clock’s falling edge.

Once you have completed this step, please have the instructor or a mentor sign off on your circuit.

Note: You cannot use a logic switch as the clock to reliably test your flip-flop. When making a transition, the contacts can “bounce” causing several edges that may be visibly undetectable to you but of real effect to the flip-flop. It is thus better to use the more reliable clock signal of the protoboard with a suitably low frequency.

Step 5: Choose Your Own Adventure

For the final step of this lab, you may choose one of the two exercises. You must complete at least one, but you do not need to complete both to earn full credit on the lab.

Once you have completed one of the options, please have the instructor or a mentor sign off on your circuit.

Option A: Clock Divider

Using a flip-flop, you can cut the frequency of a clock signal in half. Design a circuit to do this, then implement it using the flip-flop you built in step 4. If you have trouble coming up with your design, I can share a hint.

Drive the input with the protoboard’s clock input, and use logic indicators to verify that the input clock cycles twice as fast as the output clock.

Caution: There is a limit to how fast you can cycle a clock input to TTL chips and still observe the expected behavior. If you set the clock frequency too high, your flip-flop may not “settle” in its final state before the clock input changes.

Option B: Build a Simple 2x1 Register File

Using the two D latches you built for your flip-flop, implement a simple 2x1 register file (two registers, each of one bit). Your circuit should have the following inputs and outputs:

input \(A_R\): The address of the register that should be read. This will either be \(0\) for the first D latch or \(1\) for the second D latch.
input \(A_W\): The address of the register that should be written to.
input \(W\): If true, writing is enabled
input \(D\): The value that should be written to the specified register, if writing is enabled.
output \(Q\): The value of the register specified by \(A_R\).

This circuit will require a simple decoder and multiplexor. The one bit versions of these components can be built with very few gates, so try to think up a simple implementation before building your circuit.

Acknowledgments

This lab is adapted from a lab introduced to Grinnell College by Marge Coahran and updated by Janet Davis.

The circuit diagrams are Figures B.8.1 (p. B-50), B.8.2 (p B-52), and B.8.4 (p. B-53) from

Patterson D. A. & Hennessy J. L. (2014). Computer organization and design: The hardware/software interface (5th ed.). Waltham, MA: Morgan Kaufmann.

CC-BY-NC-SA This work is licensed under a Creative Commons Attribution NonCommercial ShareAlike 4.0 International License. To view a copy of this license, visit http://creativecommons.org/licenses/by-nc-sa/4.0/ or send a letter to Creative Commons, 543 Howard Street, 5th Floor, San Francisco, California, 94105, USA.