Logisim Adders

Overview

In this assignment you will build two small circuits to add one-bit binary numbers, then chain these together to produce a larger adder that can add 8-bit numbers. This assignment will give you additional practice working with Logisim, where you will continue to use subcircuits, splitters, inputs, outputs, and basic gates. You will also continue to rely on test files, enabling you to validate your circuits without manually setting inputs and checking outputs.

Grading

Your grade on this assignment will depend on the correctness of your circuits. I will use a large test suite to validate your circuits’ outputs. To receive an A on this assignment, your circuits must pass every test case. Circuits that fail fewer than 5% of the test cases will receive a B, and circuits that produce a significant number of incorrect outputs will receive a C or lower.

You may not use any Logisim components except those under the Wiring category and Gates from under the Gates category. Submissions that use disallowed components (such as Logisim’s built-in adder) will receive a zero.

Testing circuits requires that the names of inputs and outputs be specified exactly in the test files. Please pay close attention to the instructions when setting up your circuits; any submission that fails to match the specified names will likely fail most or all of the tests, resulting in a very poor grade.

Finally, some consideration will be given to the clarity of organization within your circuits. Wires and gates should be laid out in a fashion that facilitates comprehension.

Getting Started

To begin this assignment, you will need the starter circuit file and access to an installation of Logisim. If you are working on MathLAN, you can start Logisism with the following shell command:

$ java -jar /home/curtsinger/shared/logisim.jar

You can also install Logisim on your personal computer. To do this, you will need to copy the Logisim file from the MathLAN path above or download logisim.jar directly. You can then start the program with Java on your own machine.

Once you have Logisim available, download the adders.circ starter circuit file. The file is set up with three subcircuits; please pay close attention to which part of the assignment should be completed in each subcircuit. You are free to move input and output pins around and change their orientation, but please do not rename any inputs or outputs. You should not create any additional subcircuits for this assignment, and you must not rename the existing subcircuits.

Part A: Half Adder

Please complete this part of the assignment in the half-adder subcircuit.

Consider the problem of adding two bits \(x_{1}\) and \(x_{2}\):

\[\begin{array}{r} x_{1}\\ \underline{+\,x_{2}}\\ c_{o}\,s. \end{array}\]

Here \(s\) represents the “sum” or the rightmost bit, while \(c_{o}\) represents the carry (for reasons we’ll understand in the next day’s class, this is the carry out, hence the subscript).

  1. Complete the truth table for this problem, which is called a “half adder.”

    \(x_{1}\) \(x_{2}\) \(c_{o}\) \(s\)
    0 0
    0 1
    1 0
    1 1

  2. Identify the sole two gates necessary to represent the \(c_{o}\) and \(s\) outputs of a half-adder circuit.

  3. Build a half-adder circuit in Logisim. (Note that additional gates are available in the Logisim explorer pane.)

While this circuit is fairly easy to test manually (there are only four cases to try), we can instead test it automatically using Logisim’s test vectors. First, download the half-adder-tests.txt test file. To run the tests in this file, select Test Vector from the Simulate menu item in Logisim while you are in the half-adder subcircuit. Click the Load Vector button and open the test file you just downloaded. The test vector window will then show you which tests you pass or fail.

I recommend adding test cases to this file before moving on to the next part of the assignment. You can find some basic information about the test vector format in the test file itself; you can edit this file with the programming text editor of your choice.

Part B: Full Adder

Please complete this part of the assignment in the full-adder subcircuit.

Half adders work when we want to add two one-bit numbers, but we often ask computers to add much larger numbers. The processor performs multi-bit addition by chaining together a series of adders. However, a half adder basically stands in isolation because it can’t take the carry from a previous column as input in a multi-bit addition. The full adder therefore incorporates not only the two bits of a number to sum, but also the carry-out bit from the previous column as a carry-in input bit, called \(c_{i}\).

The truth table for a full adder would look like the following:

\(c_{i}\) \(x_{1}\) \(x_{2}\) \(c_{o}\) \(s\)
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

Truth Table as Test

Complete the truth table for a full adder. To make sure your subcircuit works correctly, you will ultimately test your circuit with the Test Vector tool. Enter your truth table into starter test file for this subcircuit, full-adder-tests.txt.

Implementation

Adders get used in all sorts of devices, so we’ll want to “Make the common case fast” and “Use abstraction to simplify design”, as our textbook urges. One could identify simplified, reduced functions for both \(c_{o}\) and \(s\) that minimize the number of gates using Karnaugh maps followed by Boolean algebra. However, we will find it far easier to take advantage of the hierarchical nature of addition by building your full adder from a combination of two half-adders.

The starter circuit file already has inputs named x1, x2, and ci, and outputs co and s in the “full-adder” subcircuit where they must be connected to the components you will add. These I/O pins correspond to the truth table terms \(x_{0}\), \(x_{1}\), \(c_{i}\), \(c_{o}\), and \(s\), respectively.

Implement the full adder by inserting two half-adder circuits as well as any additional wiring and/or gates that may be necessary. (Recall that adding an instance of one subcircuit to another subcircuit works exactly like adding any other component: single click on the desired component—i.e., a subcircuit—in the explorer pane and then click on the canvas to drop it into position.)

Run the tests in your full-adder-tests.txt file by selecting Test Vector from the Simulate menu item in Logisim. Click the Load Vector button and open the test file. The test vector window will then show you which tests (truth table rows) your circuit passes or fails.

Part C: 8-bit Adder

Please complete this part of the assignment in the main subcircuit.

Now that we have both full and half-adders, you should chain these subcircuits together to add a pair of 8-bit numbers. The main subcircuit has two 8-bit inputs that should be added, an 8-bit output that should contain the sum, and a carry-out output that tells us whether the most significant bit addition produced a carry that does not fit in an 8-bit result. Note that there is no carry-in input for this adder; you should not add any additional inputs or outputs to this subcircuit.

The starter circuit provides inputs and outputs with the same names as the half-adder circuit. Note that these are different inputs and outputs, all but the co output carry eight bits rather than a single bit.

Once you have an implementation of your subcircuit, you should test it. There are far too many possible inputs to test every case, but you can cover many of them using a Test Vector. The test file 8-bit-adder-tests.txt shows how you can specify multi-bit test inputs.

Once you have completed this part, please follow the instructions at the top of the assignment to submit your work.

Other Notes

Copyright © 2019–2025 Charlie Curtsinger and Jerod Weinman

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