CSC 211: Exam 3

CSC 211 - Computer Organization and Architecture - Weinman

1  Learning Outcomes

At the end of this unit you should be able to:

1. For a single-cycle datapath:
   1. Identify the portions of the datapath that are active on any given instruction
   2. Give the necessary control signals for a particular instruction
   3. Identify the critical path and minimum latency of an instruction, given the latency of individual functional units on the datapath
2. For a single-issue pipelined datapath:
   1. Identify data and control hazards
   2. Identify opportunities for data forwarding
   3. Identify when a pipeline stall is necessary
   4. Install and wire forwarding hardware
   5. Write control logic for forwarding hardware
   6. Measure throughput and latency
   7. Generate execution schedules (clock cycle diagrams) for the standard MIPS architecture
   8. Explain how exceptions are handled
3. Describe and simulate the 1-bit and 2-bit branch predictors
4. Measure the performance of various branch prediction or handling schemes
5. Find instructions that are safe to fill the branch delay slot
6. Name conditions that could generate exceptions
7. Know the difference between static multiple issue, in-order and out-of-order superscalar processing
8. Identify and categorize re-ordering hazards
9. Schedule static multiple issue processors optimally
10. Unroll loops to increase performance of multiple issue processors
11. Calculate the instructions per cycle of an execution schedule on a given processor
12. Calculate the comparative speedup of two different execution schedules

2  Study Problems

The following exercises are from Patterson and Hennessy

Chapter 4

 

(Fifth Edition)

1-16, 18

(Sixth Edition)

1-28, 31-33