# Example make file using some useful macros
# Jerod Weinman
# 29 August 2008

CC = gcc

# Name all the source files we care about
SOURCES = hello-world.c fork-exec-1.c fork-exec-2.c fork-exec-3.c

# We don't need these in this instance, but you might want them for
# something else: Create a list of all the object files by doing a
# suffix substitution on each source replacing ".c" with ".o"
OBJECTS = ${SOURCES:.c=.o}

# Create a list of all the executables by doing a suffix substitution
# on each source, replacing ".c" with the empty string ""
EXECS = ${SOURCES:.c=}

# Make everything! This runs a make for each of the executables
all: $(EXECS)
	

# Here, any of the things in EXECS will match this rule, and it says it
# depends on the .c file, which $? matches, and the $@ will end up
# being the target we gave it. Thus, if we type "make foo", then $$@.c
# will be foo.c, and $? is the dependency (also foo.c in this caes),
# and $@ will be the target "foo"
${EXECS} : $$@.c
	$(CC) $? -o $@

clean:
	rm -f $(EXECS) *~