CSC 211: Exam 1

CSC 211 - Computer Organization and Architecture - Weinman

1  Learning Outcomes

At the end of this unit you should be able to
  1. Recall the "seven great ideas" of computer architecture, and be able to match/apply them to particular examples and patterns from computer architecture or everyday analogs
  2. Calculate current, resistance, and voltage on circuits with resistors, diodes, and/or transistors using Ohm's and Kirchoff's laws
  3. Describe the behavior of NPN transistors (i.e., in various states)
  4. Implement basic logic gates in a circuit from saturating NPN transistors, using pull-up and base resistors appropriately
  5. Translate descriptions of logical problems to truth table representations
  6. Translate between truth tables and boolean logic formulas
  7. Write a boolean logic formula in the sum-of-products representation
  8. Reduce a boolean logic function using boolean laws/identities and Karnaugh maps
  9. Implement boolean logic in a circuit with logic gates (AND, OR, NOT, NAND, NOR, XOR, XNOR, etc.)
  10. Calculate the gate delay and truth table of a combinational logic circuit
  11. Construct a PLA from a sum-of-products representation
  12. Know when and how to use decoders and multiplexors to solve logic problems
  13. Convert numbers between decimal, hexadecimal, and binary (using twos complement representation)
  14. Calculate using powers of two up to 12
  15. Add and subtract numbers in binary
  16. Identify when an addition causes overflow in both signed and unsigned numbers
  17. Construct and operate an N-bit ALU (including control elements and overflow detection)
  18. Complete the characteristic table for a sequential logic circuit, including S-R latches, D latches, and D flip-flops
  19. Complete a sequential circuit timing diagram
  20. Use a register file to store and retrieve data
  21. Calculate using SI the prefixes giga-, mega-, kilo-, milli-, micro-, and nano- with respect to time
  22. Calculate using quantities given in kibibytes, mebibytes, and gibibytes
  23. Describe the bus, decoder, and multiplexor sizes for a given SRAM or DRAM configuration

2  Study Problems

The following exercises are from Patterson and Hennessy (Fifth Edition and Sixth Edition; they are identical)
Appendix B
1-2, 5-15, 17, 35-36, 39